MIT engineers have developed an innovative stacking method for electronic layers that could significantly enhance the capabilities of computer chips. As the electronics industry faces limitations on how many transistors can fit on a single chip surface, the team proposes stacking multiple layers of semiconductors, akin to constructing a high-rise instead of a ranch house. This technique aims to improve data handling and processing power for applications like AI. Traditionally, thick silicon wafers serve as the foundation for chip layers, which can hinder communication between layers. However, the researchers have created a multilayered chip design that eliminates the need for these substrates while operating at low temperatures to protect underlying circuitry. By using a new method to grow single-crystalline two-dimensional materials directly atop one another, they achieved high-quality transistors without bulky silicon scaffolds. This advancement allows better and faster communication between layers, promising substantial improvements in computing power for AI and other complex functions. The team’s work indicates that future chips could rival supercomputers in speed and data storage, paving the way for advanced AI hardware in laptops and wearable devices. The research, published in Nature, has sparked interest in commercial applications.
